A number of processors are designed to execute instructions of different lengths, such as 8-bit, 16-bit, 32-bit, and 64-bit instructions, for example. Programs for such a processor may contain a combination of these different length instructions chosen from a variable-length instruction set architecture. A processor may also have a hierarchical memory configuration with multi-levels of caches and may include an instruction cache, a data cache, and system memory, for example. The instruction cache may be configured to store and access a plurality of instructions together in cache lines. In a processor architecture supporting 16-bit and 32-bit instructions, 32-bit instructions may be stored unaligned in a cache line. Using 16-bit half-word addressing, a 32-bit instruction having its first 16-bit half-word stored in an odd 16-bit half-word address is considered not aligned. For example, a 256-bit cache line may store eight 32-bit instructions, or sixteen 16-bit instructions, or a combination of both 16-bit and 32-bit instructions. A cache line having a mix of 16-bit and 32-bit instructions may have the last 32-bit instruction crossing between two cache lines.
Also, a virtual memory system may be used that partitions the memory into pages, such as 4 kilobyte (4 k byte) pages. In such a system, the last 32-bit instruction in a cache line that crosses between two cache lines may also cross a page boundary. Each page may be assigned different attributes, which may include, for example, whether information stored on the page is cacheable or not cacheable. Thus, in a cache line having mixed instruction formats of different lengths, an instruction split across a cache line and across a page boundary may be subject to conflicting page attributes. For example, all instructions except the last instruction in the cache line may be from a first exemplary page having attributes that are cacheable, while the last instruction split across the cache line and the page boundary may have an attribute indicating a first part is cacheable while a second part is not cacheable. Such conflicts may be difficult to resolve without affecting the performance of the majority of instructions in the cache line identified with the boundary splitting last instruction.